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is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/5/2015 1 128k x36 /32 and 256k x18 4mb, ecc, synchronous pipeline d, single cycle deselect s ram october 2015 features ? internal self - timed write cycle ? individual byte write control and global write ? clock controlled, registered address, data and control ? burst sequence control using mode input ? three chip enable option for simple depth expansion and address pipelining ? common data inputs and data outputs ? auto power - down during deselect ? single cycle deselect ? s nooze mode for reduced - power standby ? jedec 100 - pin qfp , 165 - ball bga and 119 - ball bga packages ? power supply: lps : v dd 3.3v ( 5%), v ddq 3.3v/2.5v ( 5%) vps : v dd 2.5v ( 5%), v ddq 2.5v ( 5%) ? jtag boundary scan for bga packages ? industrial and automotive te mperature support ? lead - free available ? error detection and error correction description the 4 mb product family features high - speed, low - power synchronous static rams designed to provide bursta ble, high - performance memory for communication and networking applications. the is61 (64) lps/vps 128 36 ec are organized as 131,072 words by 36bits . the is61 (64) lps/vps 128 3 2 ec are organized as 131,072 words by 32bits. the is61 (64) lps/vps 25618 ec are organized as 262,144 words by 18 bits. fabricated with issi's advanced cmos technology, the device integrates a 2 - bit burst counter, high - speed sram core, and high - drive capability outputs into a single monolithic circuit. all synchronous inputs pass through registers controlled by a positive - edge - triggered single clock input . write cycles are internally self - timed and are initiated by the rising edge of the clock input. write cycles can be one to four bytes wide as controlled by the write control inputs. separate byte enables allow individual bytes to be written. the byte write operation is performed by using the byte write enable ( / bwe) input combined with one or more individual byte write signals ( / bwx). in addition, global write ( / gw) is available for writing all bytes at one time, regardless of the byte write controls. bursts can be initiated with either / adsp (address status processor) or / adsc (address status cache controller) input pins. subsequent burst addresses can be generated internally and controlled by the / adv (burst address advance) input pin. the mode pin is used to select the burst sequence order . linear burst is achieved when this pin is tied low. interleave burst is achieved when this pin is tied high or left floating . fast access time symbol parameter - 250 - 200 units t kq clock access time 2.6 3.1 ns t kc cycle time 4 5 ns f max frequency 250 200 mhz copyright ? 2015 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specification and its products at any time without no tice. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device spec ification before relying on any published information and before placing orders for products. integrated silicon solution, inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. pr oducts are not authorized f or use in such applications unless integrated silicon solution, inc. receives written assurance to its satisfaction, that: a.) the risk of injury or damage has been minimized; b.) the user assume all such risks; and c.) potential liability of integrated si licon solution, inc is adequately protected under the circumstances
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/5/2015 2 block diagram
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/5/2015 3 pin configuration 128 k x 36, 165 - ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc a /ce /bwc /bwb /ce2 /bwe /adsc /adv a nc b nc a ce2 /bwd /bwa clk /gw /oe /adsp a nc c dqpc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqpb d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc v ss nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n dqpd nc v ddq v ss nc nc nc v ss v ddq nc dqpa p nc nc a a tdi a1* tdo a a a nc r mode nc a a tms a0* tck a a a a note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bottom view 165 - ball, 13 mm x 15mm bga 11 x 15 ball array pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a synchronous address inputs /adv synchronous burst address advance /adsp synchronous address status processor /adsc synchronous address status controller mode burst sequence selection /ce,ce2,/ce2 synchronous chip enable /bwe synchronous byte write enable /bwx (x=a - d) synchronous byte write inputs /gw synchronous global write enable /oe asynchronous output enable dqx synchronous data inputs/outputs dqpx synchronous parity data i/o tck,tdi,tdo,tms jtag pins zz asynchronous power sleep mode nc no connect vdd power supply vddq i/o power supply vss ground
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/5/2015 4 128 k x 3 2 , 165 - ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc a /ce /bwc /bwb /ce2 /bwe /adsc /adv a nc b nc a ce2 /bwd /bwa clk /gw /oe /adsp a nc c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc nc d dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb e dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb f dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb g dqc dqc v ddq v dd v ss v ss v ss v dd v ddq dqb dqb h nc v ss nc v dd v ss v ss v ss v dd nc nc zz j dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa k dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa l dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa m dqd dqd v ddq v dd v ss v ss v ss v dd v ddq dqa dqa n nc nc v ddq v ss nc nc nc v ss v ddq nc nc p nc nc a a tdi a1* tdo a a a nc r mode nc a a tms a0* tck a a a a note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bottom view 165 - ball, 13 mm x 15mm bga 11 x 15 ball array pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a synchronous address inputs /adv synchronous burst address advance /adsp synchronous address status processor /adsc synchronous address status controller mode burst sequence selection /ce,ce2,/ce2 synchronous chip enable /bwe synchronous byte write enable /bwx (x=a - d) synchronous byte write inputs /gw synchronous global write enable /oe asynchronous output enable dqx synchronous data inputs/outputs tck,tdi,tdo,tm s jtag pins zz asynchronous power sleep mode nc no connect vdd power supply vddq i/o power supply vss ground
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 5 256 k x 18 , 165 - ball bga (top view) 1 2 3 4 5 6 7 8 9 10 11 a nc a /ce /bw b nc /ce2 /bwe /adsc /adv a a b nc a ce2 nc /bwa clk /gw /oe /adsp a nc c nc nc v ddq v ss v ss v ss v ss v ss v ddq nc dqp a d nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a e nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a f nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a g nc dq b v ddq v dd v ss v ss v ss v dd v ddq nc dq a h nc v ss nc v dd v ss v ss v ss v dd nc nc zz j dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc k dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc l dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc m dq b nc v ddq v dd v ss v ss v ss v dd v ddq dqa nc n dqp b nc v ddq v ss nc nc nc v ss v ddq nc nc p nc nc a a tdi a1* tdo a a a nc r mode nc a a tms a0* tck a a a a note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bottom view 165 - ball, 13 mm x 15mm bga 11 x 15 ball array pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a synchronous address inputs /adv synchronous burst address advance /adsp synchronous address status processor /adsc synchronous address status controller mode burst sequence selection /ce,ce2,/ce2 synchronous chip enable /bwe synchronous byte write enable /bwx (x=a - b) synchronous byte write inputs /gw synchronous global write enable /oe asynchronous output enable dqx synchronous data inputs/outputs dqpx synchronous parity data i/o tck,tdi,tdo,tms jtag pins zz asynchronous power sleep mode nc no connect vdd power supply vddq i/o power supply vss ground
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 6 128 k x 36, 1 19 - ball bga (top view) 1 2 3 4 5 6 7 a v ddq a a /adsp a a v ddq b nc ce2 a /adsc a / ce2 nc c nc a a v dd a a nc d dqc dqpc v ss nc v ss dqpb dqb e dqc dqc v ss / ce v ss dqb dqb f v ddq dqc v ss / oe v ss dqb v ddq g dqc dqc / bwc /adv / bwb dqb dqb h dqc dqc v ss / gw v ss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd v ss clk v ss dqa dqa l dqd dqd / bwd nc / bwa dqa dqa m v ddq dqd v ss /bwe v ss dqa v ddq n dqd dqd v ss a1* v ss dqa dqa p dqd dqpd v ss a0* v ss dqpa dqa r nc a mode v dd nc a nc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired . bottom view 119 - ball, 14 mm x 22 mm bga 7 x 17 ball array pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a synchronous address inputs /adv synchronous burst address advance /adsp synchronous address status processor /adsc synchronous address status controller mode burst sequence selection /ce,ce2,/ce2 synchronous chip enable /bwe synchronous byte write enable /bwx (x=a - d) synchronous byte write inputs /gw synchronous global write enable /oe asynchronous output enable dqx synchronous data inputs/outputs dqpx synchronous parity data i/o tck,tdi,tdo,tms jtag pins zz asynchronous power sleep mode nc no connect vdd power supply vddq i/o power supply vss ground
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 7 128 k x 3 2 , 1 19 - ball bga (top view) 1 2 3 4 5 6 7 a v ddq a a /adsp a a v ddq b nc ce2 a /adsc a / ce2 nc c nc a a v dd a a nc d dqc nc v ss nc v ss nc dqb e dqc dqc v ss / ce v ss dqb dqb f v ddq dqc v ss / oe v ss dqb v ddq g dqc dqc / bwc /adv / bwb dqb dqb h dqc dqc v ss / gw v ss dqb dqb j v ddq v dd nc v dd nc v dd v ddq k dqd dqd v ss clk v ss dqa dqa l dqd dqd / bwd nc / bwa dqa dqa m v ddq dqd v ss /bwe v ss dqa v ddq n dqd dqd v ss a1* v ss dqa dqa p dqd nc v ss a0* v ss nc dqa r nc a mode v dd nc a nc t nc nc a a a nc zz u v ddq tms tdi tck tdo nc v ddq note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bottom view 119 - ball, 14 mm x 22 mm bga 7 x 17 ball array pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a synchronous address inputs /adv synchronous burst address advance /adsp synchronous address status processor /adsc synchronous address status controller mode burst sequence selection /ce,ce2,/ce2 synchronous chip enable /bwe synchronous byte write enable /bwx (x=a - b) synchronous byte write inputs /gw synchronous global write enable /oe asynchronous output enable dqx synchronous data inputs/outputs tck,tdi,tdo,tms jtag pins zz asynchronous power sleep mode nc no connect vdd power supply vddq i/o power supply vss ground
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 8 256 k x 18 , 1 19 - ball bga (top view) 1 2 3 4 5 6 7 a v ddq a a /adsp a a v ddq b nc ce2 a /adsc a / ce2 nc c nc a a v dd a a nc d dqb nc v ss nc v ss dqpa nc e nc dqb v ss / ce v ss nc dqa f v ddq nc v ss / oe v ss dqa v ddq g nc dqb / bwb /adv v ss nc dqa h dqb nc vss / gw v ss dqa nc j v ddq v dd nc v dd nc v dd v ddq k nc dqb vss clk v ss nc dqa l dqb nc v ss nc / bwa dqa nc m v ddq dqb v ss / bwe v ss nc v ddq n dqb nc v ss a1* v ss dqa nc p nc dqpb v ss a0* v ss nc dqa r nc a mode v dd nc a nc t nc a a nc a a zz u v ddq tms tdi tck tdo nc v ddq note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. bottom view 119 - ball, 14 mm x 22 mm bga 7 x 17 ball array pin descriptions symbol pin name clk synchronous clock a0,a1 synchronous burst address inputs a synchronous address inputs /adv synchronous burst address advance /adsp synchronous address status processor /adsc synchronous address status controller mode burst sequence selection /ce,ce2,/ce2 synchronous chip enable /bwe synchronous byte write enable /bwx (x=a - b) synchronous byte write inputs /gw synchronous global write enable /oe asynchronous output enable dqx synchronous data inputs/outputs dqpx synchronous parity data i/o tck,tdi,tdo,tms jtag pins zz asynchronous power sleep mode nc no connect vdd power supply vddq i/o power supply vss ground
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 9 128k x 36 , 100pin qfp (top view) note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin descriptions symbol pin name symbol pin name clk synchronous clock /gw synchronous global write enable a0,a1 synchronous burst address inputs /oe asynchronous output enable a synchronous address inputs dqx synchronous data inputs/outputs /adv synchronous burst address advance dqpx synchronous parity data i/o /adsp synchronous address status processor zz asynchronous power sleep mode /adsc synchronous address status controller nc no connect mode burst sequence selection vdd power supply /ce,ce2,/ce2 synchronous chip enable vddq i/o power supply /bwe synchronous byte write enable vss ground /bwx (x=a - d ) synchronous byte write inputs a a /ce ce2 /bwd /bwc /bwb /bwa /ce2 vdd vss clk /gw /bwe /oe /adsc /adsp /adv a a 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 dqpc 1 80 dqpb dqc 2 79 dqb dqc 3 78 dqb vddq 4 77 vddq vss 5 76 vss dqc 6 75 dqb dqc 7 74 dqb dqc 8 73 dqb dqc 9 72 dqb vss 10 71 vss vddq 11 70 vddq dqc 12 69 dqb dqc 13 68 dqb nc 14 67 vss vdd 15 66 nc nc 16 65 vdd vss 17 64 zz dqd 18 63 dqa dqd 19 62 dqa vddq 20 61 vddq vss 21 60 vss dqd 22 59 dqa dqd 23 58 dqa dqd 24 57 dqa dqd 25 56 dqa vss 26 55 vss vddq 27 54 vddq dqd 28 53 dqa dqd 29 52 dqa dqpd 30 51 dqpa 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mode a a a a a1 a0 nc nc vss vdd nc nc a a a a a a a 128k x 36
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 10 128k x 3 2, 100pin qfp (top view) note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin descriptions symbol pin name symbol pin name clk synchronous clock /bwx (x=a - d) synchronous byte write inputs a0,a1 synchronous burst address inputs /gw synchronous global write enable a synchronous address inputs /oe asynchronous output enable /adv synchronous burst address advance dqx synchronous data inputs/outputs /adsp synchronous address status processor zz asynchronous power sleep mode /adsc synchronous address status controller nc no connect mode burst sequence selection vdd power supply /ce,ce2,/ce2 synchronous chip enable vddq i/o power supply /bwe synchronous byte write enable vss ground a a /ce ce2 /bwd /bwc /bwb /bwa /ce2 vdd vss clk /gw /bwe /oe /adsc /adsp /adv a a 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 nc 1 80 nc dqc 2 79 dqb dqc 3 78 dqb vddq 4 77 vddq vss 5 76 vss dqc 6 75 dqb dqc 7 74 dqb dqc 8 73 dqb dqc 9 72 dqb vss 10 71 vss vddq 11 70 vddq dqc 12 69 dqb dqc 13 68 dqb nc 14 67 vss vdd 15 66 nc nc 16 65 vdd vss 17 64 zz dqd 18 63 dqa dqd 19 62 dqa vddq 20 61 vddq vss 21 60 vss dqd 22 59 dqa dqd 23 58 dqa dqd 24 57 dqa dqd 25 56 dqa vss 26 55 vss vddq 27 54 vddq dqd 28 53 dqa dqd 29 52 dqa nc 30 51 nc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mode a a a a a1 a0 nc nc vss vdd nc nc a a a a a a a 128k x 32
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 11 256 k x 18, 100pin qfp (top view) note: a0 and a1 are the two least significant bits (lsb) of the address field and set the internal burst counter if burst is desired. pin descriptions symbol pin name symbol pin name clk synchronous clock / gw synchronous global write enable a0,a1 synchronous burst address inputs /oe asynchronous output enable a synchronous address inputs dqx synchronous data inputs/outputs / adv synchronous burst address advance dqpx synchronous parity data i/o /adsp synchronous address status processor zz asynchronous power sleep mode /adsc synchronous address status controller nc no connect mode burst sequence selection vdd power supply /ce,ce2,/ce2 synchronous chip enable vddq i/o power supply / bwe synchronous byte write enable vss ground /bwx (x=a - b ) synchronous byte write inputs a a /ce ce2 nc nc /bwb /bwa /ce2 vdd vss clk /gw /bwe /oe /adsc /adsp /adv a a 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 nc 1 80 a nc 2 79 nc nc 3 78 nc vddq 4 77 vddq vss 5 76 vss nc 6 75 nc nc 7 74 dqpa dqb 8 73 dqa dqb 9 72 dqa vss 10 71 vss vddq 11 70 vddq dqb 12 69 dqa dqb 13 68 dqa nc 14 67 vss vdd 15 66 nc nc 16 65 vdd vss 17 64 zz dqb 18 63 dqa dqb 19 62 dqa vddq 20 61 vddq vss 21 60 vss dqb 22 59 dqa dqb 23 58 dqa dqpb 24 57 nc nc 25 56 nc vss 26 55 vss vddq 27 54 vddq nc 28 53 nc nc 29 52 nc nc 30 51 nc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 mode a a a a a1 a0 nc nc vss vdd nc nc a a a a a a a 256k x 18
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 12 truth table synchronous truth table operation address /ce /ce2 ce2 zz adsp adsc adv write /oe clk dq deselect cycle, power - down none h x x l x l x x x l - h high - z deselect cycle, power - down none l x l l l x x x x l - h high - z deselect cycle, power - down none l h x l l x x x x l - h high - z deselect cycle, power - down none l x l l h l x x x l - h high - z deselect cycle, power - down none l h x l h l x x x l - h high - z snooze mode, power - down none x x x h x x x x x x high - z read cycle, begin burst external l l h l l x x x l l - h q read cycle, begin burst external l l h l l x x x h l - h high - z write cycle, begin burst external l l h l h l x l x l - h d read cycle, begin burst external l l h l h l x h l l - h q read cycle, begin burst external l l h l h l x h h l - h high - z read cycle, continue burst next x x x l h h l h l l - h q read cycle, continue burst next x x x l h h l h h l - h high - z read cycle, continue burst next h x x l x h l h l l - h q read cycle, continue burst next h x x l x h l h h l - h high - z write cycle, continue burst next x x x l h h l l x l - h d write cycle, continue burst next h x x l x h l l x l - h d read cycle, suspend burst current x x x l h h h h l l - h q read cycle, suspend burst current x x x l h h h h h l - h high - z read cycle, suspend burst current h x x l x h h h l l - h q read cycle, suspend burst current h x x l x h h h h l - h high - z write cycle, suspend burst current x x x l h h h l x l - h d write cycle, suspend burst current h x x l x h h l x l - h d note: 1. x means dont care. h means logic high. l means logic low. 2. for write, l means one or more byte write enable signals ( / bwa - d) and / bwe are low or / gw is low. / write = h for all / bwx, / bwe, / gw high. 3. / bwa enables writes to dqas and dqpa. / bwb enables writes to dqbs and dqpb. / bwc enables writes to dqcs and dqpc. / bwd enables writes to dqds and dqpd. dqpa and dqpb are avail able on the x18 version. dqpa - dqpd are available on the x36 version. 4. all inputs except / oe and zz must meet setup and hold times around the rising edge (low to high) of clk. 5. wait states are inserted by suspending burst. 6. for a write operation following a read operation, / oe must be high before the input data setup time and held high during the input data hold time. 7. this device contains circuitry that will ensure the outputs will be in high - z during power - up. 8. / adsp low alwa ys initiates an internal read at the l - h edge of clk. a write is performed by setting one or more byte write enable signals and / bwe low or / gw low for the subsequent l - h edge of clk. see write timing diagram for clarification.
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 13 partial truth table operation / gw / b we /bwa /bwb /bwc /bwd read h h x x x x read h l h h h h write byte a h l l h h h write byte b h l h l h h write byte c h l h h l h write byte d h l h h h l write all bytes h l l l l l write all bytes l x x x x x notes: 1. x means "don't care". 2. all inputs in this table must beet setup and hold time around the rising edge of clk. address sequence in burst mode interleaved burst address table (mode = v dd or nc) external address 1st burst address 2nd burst address 3rd burst address a1 a0 a1 a0 a1 a0 a1 a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = v ss ) power up sequence vddq vdd 1 i/o pins 2 notes: 1. vdd can be applied at the same time as vddq 2. applying i/o inputs is recommended after vddq is stable. the inputs of the i/o pins can be applied at the same time as vddq a s long as vih (level of i/o pins) is lower than vddq. a1', a0' = 1,1 0,0 1,0 0,1
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 14 error detection and correction ? i ndependent ecc with hamming code for each byte. ? detect and correct one bit error per byte. ? better reliability than parity code schemes that could detect error bit but not correct it. ? backward compatible : drop in replacement to current in industry standard devices without ecc. absolute maximum ratings and operating range absolute maximum ratings symbol parameter lps value vps value unit t stg storage temperature C 65 to +150 C 65 to +150 c p d power dissipation 1.6 1.6 w i out output current (per i/o) 100 100 ma v in , v out voltage relative to vss for i/o pins C 0.5 to v ddq +0. 5 C 0.3 to v ddq + 0.3 v v dd voltage relative to vss for address and control inputs C 0.5 to v dd +0.5 C 0.3 to v dd + 0.3 v notes: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. this device contains circuitry to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high - impedance circuit. 3. this device contains circuitry that will ensure the output devices are in high - z at power up. operating range option range vdd vddq ambient temperature is61lpsxxxxx commercial 3.3v 5% 3.3v / 2.5v 5% 0c to +70c industrial 3.3v 5% 3.3v / 2.5v 5% - 40c to +85c is61vpsxxxxx commercial 2.5v 5% 2.5v 5% 0c to +70c industrial 2.5v 5% 2.5v 5% - 40c to +85c is64lpsxxxxx automotive 3.3v 5% 3.3v / 2.5v 5% - 40c to +125c is64vpsxxxxx automotive 2.5v 5% 2.5v 5% - 40c to +125c
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 15 characteristics dc electrical characteristics (over operating temperature r ange) symbol parameter test conditions 3.3v 2.5v unit min. max. min. max. voh output high voltage ioh= - 4.0 ma(3.3v) 2.4 2.0 v ioh= C 1.0 ma(2.5v ) vol output low voltage iol=8.0 ma(3.3v) 0.4 0.4 v iol=1.0 ma(2.5v ) vih input high voltage 2.0 vdd+0.3 1.7 vdd+0.3 v vil input low voltage C 0.3 0.8 C 0.3 0.7 v ili input leakage current vssvinvdd C 5 5 C 5 5 a ilo output leakage current vssvoutvddq,/oe=vih C 5 5 C 5 5 a notes: 1. all voltages referenced to ground. 2. overshoot: 3.3v and 2.5v: vih (ac) vdd + 1.5v (pulse width less than tkc /2) 1.8v: vih (ac) vdd + 0.5v (pulse width less than tkc /2) 3. undershoot: 3.3v and 2.5v: vil (ac) - 1.5v (pulse width less than tkc /2) 1.8v: vil (ac) - 0.5v (pulse width less than tkc /2) power supply characteristics (over operating range) sym bol parameter test conditions temp. range - 250 - 200 unit max max x18 x 36 /32 x18 x36 /32 icc ac operating, supply current device selected, oe = vih, zz vil,all inputs 0.2v or vdd C 0.2v,cycle time tkc min. com. 22 5 22 5 20 0 20 0 ma ind. 25 0 25 0 21 0 21 0 auto 27 5 27 5 22 5 22 5 isb standby current ttl input device deselected,vdd = max.,all inputs vil or vih,zz vil, f = max. com. 9 0 9 0 9 0 9 0 ma ind. 10 0 10 0 10 0 10 0 auto 12 0 12 0 12 0 12 0 isb1 standby current cmos input device deselected,vdd = max.,vin vss + 0.2v or vdd C 0.2v,f = 0 com. 7 0 7 0 7 0 7 0 ma ind. 7 5 7 5 7 5 7 5 auto 9 0 9 0 9 0 9 0 note: 1. mode pin has an internal pullup and should be tied to vdd or vss . it exhibits 100a maximum leakage current when tied to vss+0.2v or vdd C 0.2v. capacitance symbol parameter conditions max. unit c in input capacitance v in = 0v 6 pf c out input/output capacitance v out = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: ta = 25c, f = 1 mhz, vdd = 3.3v.
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 16 read/write cycle switching characteristics (over operating range) symbol parameter - 250 - 200 unit min. max. min. max. f max clock frequency kc cycle time 4 kh clock high time 1.7 kl clock low time 1.7 kq clock access time kqx (2) clock high to output invalid 0.8 kqlz (2,3) clock high to output low - z 0.8 kqhz (2,3) clock high to output high - z oeq output enable to output valid oelz (2,3) output enable to output low - z 0 oehz (2,3) output disable to output high - z as address setup time 1.2 ss address status setup time 1.2 ws read/write setup time 1.2 ces chip enable setup time 1.2 se clock enable setup time 1.2 advs address advance setup time 1.2 ds data setup time 1.2 sh address status hold time 1.2 ah address hold time 0.3 he clock enable hold time 0.3 wh write hold time 0.3 ceh chip enable hold time 0.3 advh address advance hold time 0.3 dh data hold time 0.3 power (4) vdd (typical) to first access 1 notes: 1. configuration signal mode is static and must not change during normal operation. 2. guaranteed but not 100% tested. this parameter is periodically sampled. 3. tested with load in figure 2. 4. tpower is the time that the power needs to be supplied above vdd (min) initially before read or write operation can be initia ted.
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 17 3.3v i/o ac test conditions parameter unit input pulse level 0v to 3.0v input rise and fall times 1.5 ns input and output timing and reference level 1.5v v tt 1.5v v load 3.3v r1, r2 317, 351 output load see figures 1 and 2 2.5v i/o ac test conditions parameter unit input pulse level 0v to 2.5v input rise and fall times 1.5 ns input and output timing and reference level 1.25v v tt 1.25v v load 2.5v r1, r2 1667, 1538 output load see figures 1 and 2 i/o output load equivalent 50 ? output z o =50 ? v tt v load output 5 pf including jig and scope r2 r1 figure1 figure 2
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 18 read cycle timing
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 19 write cycle timing high - z dataout address datain / adsc / adsp / adv clk / bwe / ce2 ce2 / bwx / oe / gw / ce high - z tss tas single write tds tdh / adv must be inactive for / adsp write tws tkh tkc tkl ce2 and / ce2 only sampled with / adsp or / adsc / ce masks / adsp burst write tavs / adsp is blocked by / ce inactive / adsc initiate s write write wr3 wr3 unselected unselected with ce2 t s h t av h wr 2 wr 1 t a h t w h t w h tws wr 2 wr 1 tws t w h t w h tws t ces t ceh t ceh t ces t ceh t ces / bw 1 - / bw 4 only are applied to first cycle of wr2 1a 2a 2b 2c 2d 3a
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 20 snooze mode electrical characteristics symbol parameter conditions temperature range min. max. unit isb2 current during snooze mode zz vih com. 35 ma ind. 40 auto. 60 tpds zz active to input ignored 2 cycle tpus zz inactive to input sampled 2 cycle tzzi zz active to snooze current 2 cycle trzzi zz inactive to exit snooze current 0 ns sleep mode timing clk zz isupply all inputs (except zz) tpds tzzi isb2 trzzi deselect or read only deselect or read only zz setup cycle normal operation cycle outputs (q) don't care high - z zz recovery cycle tp u s
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 21 ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee standard 1149.1, the sram contains a tap controller, instruction register, boundary scan re gister, bypass register, and id register. the tap controller has a standard 16 - state machine that resets internally on power - up. therefore, a trst signal is not required disabling the jtag feature the sram can operate without using the jtag feature. to disable the tap controller, tck must be tied low (vss) to prevent clocking of the device. tdi and tms are internally pulled up and may be left disconnected. they may alternately be connected to vdd through a pull - up resistor. tdo should be left disconnecte d. on power - up, the device will come up in a reset state, which will not interfere with device operation. test access port signal list: 1. test clock (tck) this signal uses vdd as a power supply. the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. 2. test mode select (tms) this signal uses vdd as a power supply. the tms input is used to send commands to the tap controller and is sampled on the rising edge of tck. 3. test data - in (tdi) this signal uses vdd as a power supply. the tdi input is used to serially input test instructions and information into the registers and can be connected to the input of any of the registers. the register between tdi an d tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is connected to the most significant bit (msb) of any register. for more information regarding instruction register loading, please see the tap controller state diagra m. 4. test data - out (tdo) this signal uses vddq as a power supply. the tdo output ball is used to serially clock test instructions and data out from the registers. the tdo output driver is only active during the shift - ir and shift - dr tap controller states . in all other states, the tdo pin is in a high - z state. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. for more information, please see the tap controller state diagram.
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 22 tap controller state and block diagram tap controller state machine b y p a s s r e g i s t e r ( 1 b i t ) i d e n t i f i c a t i o n r e g i s t e r ( 3 2 b i t s ) i n s t r u c t i o n r e g i s t e r ( 3 b i t s ) t a p c o n t r o l l e r t d o t m s t c k t d i c o n t r o l s i g n a l s b o u n d a r y s c a n r e g i s t e r ( 7 5 b i t s ) . . . t e s t l o g i c r e s e t s e l e c t d r r u n t e s t i d l e 0 1 1 c a p t u r e d r 0 1 0 0 1 0 1 1 0 s h i f t d r e x i t 1 d r p a u s e d r e x i t 2 d r 1 1 u p d a t e d r 0 s e l e c t i r 1 c a p t u r e i r 0 1 0 0 1 0 1 s h i f t i r e x i t 1 i r p a u s e i r e x i t 2 i r 1 1 u p d a t e i r 0 0 0 1 0 1 0
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 23 performing a tap reset a reset is performed by forcing tms high (vdd) for five rising edges of tck. reset may be performed while the sram is operating and does not affect its operation. at power - up, the tap is internally reset to ensure that tdo comes up in a high - z state. tap registers registers are connected between the tdi and tdo pins and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction registers. data is serially loaded into the tdi pin on the rising edge of tck and output on the tdo pin on the falling edge of tck. 1. instruction register this register is loaded during the updat e - ir state of the tap controller. at power - up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap con troller is in the capture - ir state, the two lsbs are loaded with a binary 01 pattern to allow for fault isolation of the board - level serial test data path. 2. bypass register the bypass register is a single - bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. 3. boundary scan register the boundary scan register is connected to all the input and bid irectional balls on the sram. several balls are also included in the scan register to reserved balls. the boundary scan register is loaded with the contents of the sram input and output ring when the tap controller is in the capture - dr state and is then pl aced between the tdi and tdo balls when the controller is moved to the shift - dr state. each bit corresponds to one of the balls on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. 4. identification (id) regis ter the id register is loaded with a vendor - specific, 32 - bit code during the capture - dr state when the idcode command is loaded in the instruction register. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shif t - dr state. scan register sizes register name bit size instruction 3 bypass 1 id 32 boundary scan 75 tap instruction set many instructions are possible with an eight - bit instruction register and all valid combinations are listed in the tap instruction code table. all other instruction codes that are not listed on this table are reserved and should not be used. instructions a re loaded into the tap controller during the shift - ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted from the instruction register through the
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 24 tdi and tdo pins. to execute an instruction once it is shifted in, the tap controller must be moved into the update - ir state. 1. extest the extest instruction allows circuitry external to the component package to be tested. boundary - scan register cells at output balls are used to apply a test vector, wh ile those at input balls capture test results. typically, the first test vector to be applied using the extest instruction will be shifted into the boundary scan register using the preload instruction. thus, during the update - ir state of extest, the output driver is turned on, and the preload data is driven onto the output balls . however, this product forces all sram outputs to high - z state and this instruction is not 1149.1 compliant. 2. idcode the idcode instruction causes a vendor - specific, 32 - bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift - dr state. the idcode instruction is loaded into the instruction register upon power - up or whenever the tap controller is given a test logic reset state. 3. sample z if the sample - z instruction is loaded in the instruction register, all sram outputs are forced to an inactive drive state (high - z), moving the tap controller into the capture - dr state loads the data in the srams input into the boundary scan register, and the boundary scan register is connected between tdi and tdo when the tap controller is moved to the shift - dr state. 4. sample/preloa d when the sample/preload instruction is loaded into the instruction register and the tap controller is in the capture - dr state, a snapshot of data on the inputs and bidirectional balls is captured in the boundary scan register. the user must be aware that the tap controller clock can only operate at a frequency up to 50 mhz, while the sram clock operates significantly faster. because there is a large difference between the clock frequencies, it is possible that during the capture - dr state, an input or outp ut will undergo a transition. the tap may then try to capture a signal while in transition. this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to ensure that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controllers capture setup plus hold time. the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/ preload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck# captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift - dr state. this places the boundary scan register between the tdi and tdo balls. 6. bypass when the bypass instruction is loaded in the instruction register and the tap is placed in a shift - dr state, the bypass register is placed between tdi and tdo. the advantage of the bypass instruction is that it shortens the boundary scan path when multiple devices are connected together on a board. 7. private do not use these instructions. they are reserved for future use and engineering mode.
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 25 jtag tap dc electrical characteristics ( v ddq =3.3v operating range ) parameter symbol min max units notes jtag input high voltage v ih1 2.0 v dd +0.3 v jtag input low voltage v il1 C oh1 2.4 - v |i oh1 | = 2ma jtag output low voltage v ol1 - 0. 4 v i ol1 = 2m a jtag output high voltage v oh2 2. 9 - v |i oh 2 | =100u a jtag output low voltage v ol2 - 0.2 v i ol 2 =100ua jtag input load current i x - 10 +10 u a 0 vin v dd notes: 1. all voltages referenced to vss (gnd) ; all jtag inputs and outputs are lvttl - compatible . jtag tap dc electrical characteristics (v ddq =2.5 v operating range ) parameter symbol min max units notes jtag input high voltage v ih1 1.7 v dd +0.3 v jtag input low voltage v il1 C oh1 2.0 - v |i oh1 | = 2ma jtag output low voltage v ol1 - 0.4 v i ol1 = 2m a jtag output high voltage v oh2 2. 1 - v |i oh 2 | =100u a jtag output low voltage v ol2 - 0.2 v i ol 2 =100ua jtag input load current i x - 10 +10 u a 0 vin v dd notes: 2. all voltages referenced to vss (gnd) ; all jtag inputs and outputs are lvttl - compatible . jtag ac test conditions (over the operating temperature range) parameter symbol 2.5v option 3.3v option units input pulse high level v ih1 2.5 3.0 v input pulse low level v il1 0 0 v input r ise and fall t ime t r1 1.5 1.5 ns test load termination supply voltage v ref 1.25 1.5 v input and output timing reference level v ref 1.25 1.5 v tap output load equivalent v ref test comparator output 50 o 20 pf 50 o v ref
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 26 jtag ac characteristics (over the operating temperature range) parameter symbol min max units tck cycle time t thth 10 0 C thtl 4 0 C tlth 4 0 C mvth 10 C thmx 10 C dvth 10 C thdx 10 C tlov C jtag timing diagram t c k t m s t t h t h t t h t l t t l t h t t h m x t m v t h t d i t d o t t l o v t t h d x t d v t h
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 27 instruction set code instruction tdo output notes 000 extest boundary scan register 2, 6 001 idcode 32 - bit identification register 010 sample - z boundary scan register 1, 2 011 private do not use 5 100 sample (/preload) boundary scan register 4 101 private do not use 5 110 private do not use 5 111 bypass bypass register 3 notes: 1. places qs in high - z in order to sample all input data, regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift - dr state. 4. sample instruction does not place qs in high - z. 5. this instruction is reserved. invoking this instruction will cause improper sram functionality. 6. this extest is not ieee 1149.1 - compliant. by default, it places q in high - z. if the internal register on the sca n chain is set high, q will be updated with information loaded via a previous sample instruction. the actual transfer occurs during the update ir state after extest is l oaded. the value of the internal register can be changed during sample and extest only. id register definition instruction field description 128 k x 36 /32 256 k x 18 revision number (31:28) reserved for version number. xxxx xxxx device depth (27:23) defines depth of sram. 128 k or 256 k 0011 0 00111 device width (22:18) defines width of the sram. x36 /32 or x18 00100 00011 issi device id (17:12) reserved for future use. xxxxx xxxxx issi jedec id (11:1) allows unique identification of sram vendor. 00011010101 00011010101 id register presence (0) indicate the presence of an id register. 1 1
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 28 boundary scan order 165 bga 119 bga x36 /32 x18 x36 /32 x18 bit # signal bump id signal bump id bit # signal bump id signal bump id 1 mode 1r mode 1r 1 mode 3r mode 3r 2 nc 6n nc 6n 2 nc 4l nc 4l 3 nc 11p nc 11p 3 nc 7r nc 7r 4 a 8p a 8p 4 a 4 t a 2 t 5 a 8r a 8r 5 a 3 t a 3 t 6 a 9r a 9r 6 a 5b a 5b 7 a 9p a 9p 7 a 5c a 5c 8 a 10p a 10p 8 a 5 a a 5 a 9 a 10r a 10r 9 a 5t a 5t 10 a 11r a 11r 10 a 6r a 6r 11 zz 11h zz 11h 11 zz 7t zz 7t 12 dqpa 11n nc 11n 12 dq p a 6p nc 6p 13 dqa 11m nc 11m 13 dqa 7n nc 7 n 14 dqa 11l nc 11l 14 dqa 6m nc 6m 15 dqa 11k nc 11k 15 dqa 7 p nc 7l 16 dqa 11j nc 11j 16 dqa 6 n nc 6k 17 dqa 10m dqa 10m 17 dqa 7l dqa 7p 18 dqa 10l dqa 10l 18 dqa 6 k dqa 6 n 19 dqa 10k dqa 10k 19 dqa 6l dqa 6l 20 dqa 10j dqa 10j 20 dqa 7 k dqa 7 k 21 dq b 11g dqa 11g 21 dqb 6h dqa 6h 22 dq b 11f dqa 11f 22 dqb 7g dqa 7g 23 dq b 11e dqa 11e 23 dqb 7 h dqa 6f 24 dq b 11d dqa 11d 24 dqb 6f dqa 7 e 25 dqb 10g dqpa 11c 25 dq b 7e dqpa 6d 26 dqb 10f nc 10f 26 dqb 6g nc 6g 27 dqb 10e nc 10e 27 dqb 6e nc 6e 28 dqb 10d nc 10d 28 dqb 7d nc 7d 29 dqpb 11c nc 10g 29 dq p b 6d nc 7h 30 nc 11a a 11a 30 nc 6t a 6t 31 a 10a a 10a 31 a 6 a a 6 a 32 a 10b a 10b 32 a 6c a 6c 33 /adv 9a /adv 9a 33 / adv 4g / adv 4g 34 /adsp 9b /adsp 9b 34 / ads p 4a / ads p 4a 35 /adsc 8a /adsc 8a 35 / ad sc 4b / ad sc 4b 36 /oe 8b /oe 8b 36 / oe 4f / oe 4f 37 /bwe 7a /bwe 7a 37 / bwe 4m / bw e 4m 38 /gw 7b /gw 7b 38 / gw 4h / gw 4h 39 clk 6b clk 6b 39 clk 4k clk 4k 40 nc 11b nc 11b 40 nc 7c nc 7c continue next pa ge
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 29 165 bga 119 bga x36 /32 x18 x36 /32 x18 bit # signal bump id signal bump id bit # signal bump id signal bump id 41 nc 1a nc 1a 41 nc 1b nc 1b 42 /ce2 6a /ce2 6a 42 / c e2 6b / ce2 6b 43 /bwa 5b /bwa 5b 43 / bwa 5l / bwa 5l 44 /bwb 5a nc 5a 4 4 / bwb 5g nc 5g 45 /bwc 4a /bwb 4a 45 / bwc 3 g / bwb 3g 46 /bwd 4b nc 4b 46 / bwd 3l nc 3l 47 ce2 3b ce2 3b 47 ce2 2b ce2 2b 48 /ce 3a /ce 3a 48 / ce 4e / ce 4 e 49 a 2a a 2a 4 9 a 3a a 3a 50 a 2b a 2b 5 0 a 2a a 2a 51 nc 1b nc 1b 5 1 nc 1c nc 1c 52 dqpc 1c nc 1c 5 2 dq p c 2d nc 2d 53 dqc 1d nc 1d 5 3 dq c 1e nc 1e 54 dqc 1e nc 1e 5 4 dq c 2f nc 2f 55 dqc 1f nc 1f 5 5 dq c 1d nc 1g 56 dqc 1g nc 1g 5 6 dq c 2e nc 2h 57 dqc 2d dqb 2d 5 7 dq c 1g dq b 1d 58 dqc 2e dqb 2e 5 8 dq c 2h dq b 2e 59 dqc 2f dqb 2f 5 9 dq c 2g dq b 2g 60 dqc 2g dqb 2g 6 0 dq c 1h dq b 1h 61 dq d 1j dqb 1j 6 1 dq d 2k dq b 2k 62 dq d 1k dqb 1k 6 2 dq d 1l dq b 1l 63 dqd 1l dqb 1l 6 3 dq d 1k dq b 2m 64 dq d 1m dqb 1m 6 4 dq d 2m dq b 1n 65 dqd 2j dqpb 1n 6 5 dq d 1n dqp b 2p 66 dqd 2k nc 2k 6 6 dq d 2l nc 2l 67 dqd 2l nc 2l 6 7 dq d 2n nc 2n 68 dqd 2m nc 2m 6 8 dq d 1p nc 1p 69 dqpd 1n nc 2j 6 9 dq p d 2p nc 1k 70 a 3p a 3p 7 0 a 2r a 2r 71 a 3r a 3r 7 1 a 2c a 2c 72 a 4r a 4r 7 2 a 3b a 3b 73 a 4p a 4p 7 3 a 3c a 3c 74 a1 6p a1 6p 7 4 a1 4 n a1 4 n 75 a0 6r a0 6r 7 5 a 0 4 p a 0 4 p note : dqp a, dqp b, dqp c, and dqpd pins of x36 io option are nc of x32 io option.
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 30 ordering information the ordering code information of the product family
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 31 commercial range: 0c to 70 c vdd speed x36 x32 x18 package vdd =3.3v vddq=2.5v or vddq=3.3v 250mhz is61lps 12836ec - 250tq is61lps 12832ec - 250tq is61lps 25618ec - 250tq 100 qfp is61lps 12836ec - 250b3 is61lps 12832ec - 250b3 is61lps 25618ec - 250b3 165 bga is61lps 12836ec - 250b2 is61lps 12832ec - 250b2 is61lps 25618ec - 250b2 119 bga is61lps 12836ec - 250tql is61lps 12832ec - 250tql is61lps 25618ec - 250tql 100 qfp , lead - free is61lps 12836ec - 250b3l is61lps 12832ec - 250b3l is61lps 25618ec - 250b3l 165 bga , lead - free is61lps 12836ec - 250b2l is61lps 12832ec - 250b2l is61lps 25618ec - 250b2l 119 bga , lead - free 200mhz is61lps 12836ec - 200tq is61lps 12832ec - 200tq is61lps 25618ec - 200tq 100 qfp is61lps 12836ec - 200b3 is61lps 12832ec - 200b3 is61lps 25618ec - 200b3 165 bga is61lps 12836ec - 200b2 is61lps 12832ec - 200b2 is61lps 25618ec - 200b2 119 bga is61lps 12836ec - 200tql is61lps 12832ec - 200tql is61lps 25618ec - 200tql 100 qfp , lead - free is61lps 12836ec - 200b3l is61lps 12832ec - 200b3l is61lps 25618ec - 200b3l 165 bga , lead - free is61lps 12836ec - 200b2l is61lps 12832ec - 200b2l is61lps 25618ec - 200b2l 119 bga , lead - free vdd =2.5v vddq=2.5v 250mhz is61vps 12836ec - 250tq is61vps 12832ec - 250tq is61vps 25618ec - 250tq 100 qfp is61vps 12836ec - 250b3 is61vps 12832ec - 250b3 is61vps 25618ec - 250b3 165 bga is61vps 12836ec - 250b2 is61vps 12832ec - 250b2 is61vps 25618ec - 250b2 119 bga is61vps 12836ec - 250tql is61vps 12832ec - 250tql is61vps 25618ec - 250tql 100 qfp , lead - free is61vps 12836ec - 250b3l is61vps 12832ec - 250b3l is61vps 25618ec - 250b3l 165 bga , lead - free is61vps 12836ec - 250b2l is61vps 12832ec - 250b2l is61vps 25618ec - 250b2l 119 bga , lead - free 200mhz is61vps 12836ec - 200tq is61vps 12832ec - 200tq is61vps 25618ec - 200tq 100 qfp is61vps 12836ec - 200b3 is61vps 12832ec - 200b3 is61vps 25618ec - 200b3 165 bga is61vps 12836ec - 200b2 is61vps 12832ec - 200b2 is61vps 25618ec - 200b2 119 bga is61vps 12836ec - 200tql is61vps 12832ec - 200tql is61vps 25618ec - 200tql 100 qfp , lead - free is61vps 12836ec - 200b3l is61vps 12832ec - 200b3l is61vps 25618ec - 200b3l 165 bga , lead - free is61vps 12836ec - 200b2l is61vps 12832ec - 200b2l is61vps 25618ec - 200b2l 119 bga , lead - free
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 32 indus trial range: - 40c to 85c vdd speed x36 x32 x18 package vdd =3.3v vddq=2.5v or vddq=3.3v 250mhz is61lps 12836ec - 250tqi is61lps 12832ec - 250tqi is61lps 25618ec - 250tqi 100 qfp is61lps 12836ec - 250b3i is61lps 12832ec - 250b3i is61lps 25618ec - 250b3i 165 bga is61lps 12836ec - 250b2i is61lps 12832ec - 250b2i is61lps 25618ec - 250b2i 119 bga is61lps 12836ec - 250tqli is61lps 12832ec - 250tqli is61lps 25618ec - 250tqli 100 qfp , lead - free is61lps 12836ec - 250b3li is61lps 12832ec - 250b3li is61lps 25618ec - 250b3li 165 bga , lead - free is61lps 12836ec - 250b2li is61lps 12832ec - 250b2li is61lps 25618ec - 250b2li 119 bga , lead - free 200mhz is61lps 12836ec - 200tqi is61lps 12832ec - 200tqi is61lps 25618ec - 200tqi 100 qfp is61lps 12836ec - 200b3i is61lps 12832ec - 200b3i is61lps 25618ec - 200b3i 165 bga is61lps 12836ec - 200b2i is61lps 12832ec - 200b2i is61lps 25618ec - 200b2i 119 bga is61lps 12836ec - 200tqli is61lps 12832ec - 200tqli is61lps 25618ec - 200tqli 100 qfp , lead - free is61lps 12836ec - 200b3li is61lps 12832ec - 200b3li is61lps 25618ec - 200b3li 165 bga , lead - free is61lps 12836ec - 200b2li is61lps 12832ec - 200b2li is61lps 25618ec - 200b2li 119 bga , lead - free vdd =2.5v vddq=2.5v 250mhz is61vps 12836ec - 250tqi is61vps 12832ec - 250tqi is61vps 25618ec - 250tqi 100 qfp is61vps 12836ec - 250b3i is61vps 12832ec - 250b3i is61vps 25618ec - 250b3i 165 bga is61vps 12836ec - 250b2i is61vps 12832ec - 250b2i is61vps 25618ec - 250b2i 119 bga is61vps 12836ec - 250tqli is61vps 12832ec - 250tqli is61vps 25618ec - 250tqli 100 qfp , lead - free is61vps 12836ec - 250b3li is61vps 12832ec - 250b3li is61vps 25618ec - 250b3li 165 bga , lead - free is61vps 12836ec - 250b2li is61vps 12832ec - 250b2li is61vps 25618ec - 250b2li 119 bga , lead - free 200mhz is61vps 12836ec - 200tqi is61vps 12832ec - 200tqi is61vps 25618ec - 200tqi 100 qfp is61vps 12836ec - 200b3i is61vps 12832ec - 200b3i is61vps 25618ec - 200b3i 165 bga is61vps 12836ec - 200b2i is61vps 12832ec - 200b2i is61vps 25618ec - 200b2i 119 bga is61vps 12836ec - 200tqli is61vps 12832ec - 200tqli is61vps 25618ec - 200tqli 100 qfp , lead - free is61vps 12836ec - 200b3li is61vps 12832ec - 200b3li is61vps 25618ec - 200b3li 165 bga , lead - free is61vps 12836ec - 200b2li is61vps 12832ec - 200b2li is61vps 25618ec - 200b2li 119 bga , lead - free
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 33 automotive(a3) range: - 40c to 12 5c vdd speed x36 x32 x18 package vdd =3.3v vddq=2.5v or vddq=3.3v 250mhz is64lps 12836ec - 250tqa3 is64lps 12832ec - 250tqa3 is64lps 25618ec - 250tqa3 100 qfp is64lps 12836ec - 250b3a3 is64lps 12832ec - 250b3a3 is64lps 25618ec - 250b3a3 165 bga is64lps 12836ec - 250b2a3 is64lps 12832ec - 250b2a3 is64lps 25618ec - 250b2a3 119 bga is64lps 12836ec - 250tqla3 is64lps 12832ec - 250tqla3 is64lps 25618ec - 250tqla3 100 qfp , lead - free is64lps 12836ec - 250b3la3 is64lps 12832ec - 250b3la3 is64lps 25618ec - 250b3la3 165 bga , lead - free is64lps 12836ec - 250b2la3 is64lps 12832ec - 250b2la3 is64lps 25618ec - 250b2la3 119 bga , lead - free 200mhz is64lps 12836ec - 200tqa3 is64lps 12832ec - 200tqa3 is64lps 25618ec - 200tqa3 100 qfp is64lps 12836ec - 200b3a3 is64lps 12832ec - 200b3a3 is64lps 25618ec - 200b3a3 165 bga is64lps 12836ec - 200b2a3 is64lps 12832ec - 200b2a3 is64lps 25618ec - 200b2a3 119 bga is64lps 12836ec - 200tqla3 is64lps 12832ec - 200tqla3 is64lps 25618ec - 200tqla3 100 qfp , lead - free is64lps 12836ec - 200b3la3 is64lps 12832ec - 200b3la3 is64lps 25618ec - 200b3la3 165 bga , lead - free is64lps 12836ec - 200b2la3 is64lps 12832ec - 200b2la3 is64lps 25618ec - 200b2la3 119 bga , lead - free vdd =2.5v vddq=2.5v 250mhz is64vps 12836ec - 250tqa3 is64vps 12832ec - 250tqa3 is64vps 25618ec - 250tqa3 100 qfp is64vps 12836ec - 250b3a3 is64vps 12832ec - 250b3a3 is64vps 25618ec - 250b3a3 165 bga is64vps 12836ec - 250b2a3 is64vps 12832ec - 250b2a3 is64vps 25618ec - 250b2a3 119 bga is64vps 12836ec - 250tqla3 is64vps 12832ec - 250tqla3 is64vps 25618ec - 250tqla3 100 qfp , lead - free is64vps 12836ec - 250b3la3 is64vps 12832ec - 250b3la3 is64vps 25618ec - 250b3la3 165 bga , lead - free is64vps 12836ec - 250b2la3 is64vps 12832ec - 250b2la3 is64vps 25618ec - 250b2la3 119 bga , lead - free 200mhz is64vps 12836ec - 200tqa3 is64vps 12832ec - 200tqa3 is64vps 25618ec - 200tqa3 100 qfp is64vps 12836ec - 200b3a3 is64vps 12832ec - 200b3a3 is64vps 25618ec - 200b3a3 165 bga is64vps 12836ec - 200b2a3 is64vps 12832ec - 200b2a3 is64vps 25618ec - 200b2a3 119 bga is64vps 12836ec - 200tqla3 is64vps 12832ec - 200tqla3 is64vps 25618ec - 200tqla3 100 qfp , lead - free is64vps 12836ec - 200b3la3 is64vps 12832ec - 200b3la3 is64vps 25618ec - 200b3la3 165 bga , lead - free is64vps 12836ec - 200b2la3 is64vps 12832ec - 200b2la3 is64vps 25618ec - 200b2la3 119 bga , lead - free ? note : not all automotive options listed are currently available. please contact issi for parts
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 34 package outline drawing 100 qfp (14x20x1.4mm)
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 35 119 bga (14x22x2.15 mm)
is61(4) lps 12836ec/is61(4) vps 12836ec/is61(4) lps 12832ec is61(4) vps 12832ec / is61(4) lps 25618ec/is61(4) vps 25618ec integrated silicon solution, inc. - www.issi.com rev. d1 10/2/2015 36 165 bga (13x15x1.2 mm)

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